1. Field of the Invention
The present invention relates to a semiconductor memory device which requires refresh operation and a refresh control method, and particularly to a semiconductor memory device which can control the refresh operation on the occasion of executing the refresh operation as an internal access operation independent of an external access operation and a refresh control method.
2. Description of Related Art
A semiconductor memory device represented by a dynamic random access memory (hereinafter referred to as DRAM) is required to periodically perform the refresh operation in order to maintain the data stored in a memory cell.
FIG. 10 shows operation waveforms in the so-called self-refresh operation which means the automatic refresh operation executed in every predetermined period in the standby state among the ordinary refresh operations in the related art. FIG. 10(A) indicates the control in the case of the asynchronous DRAM in which the self-refresh operation is executed in the CAS before RAS refresh operation. Namely, the self-refresh operation is controlled, for the external control signals /RAS and /CAS, with a signal transition sequence opposed to that of the ordinary access operation in which the /CAS signal is transitioned to a low logic level before the low logic level transition of the /RAS signal. The state of self-refresh operation can be maintained while the external control signals /RAS, /CAS are in the low logic level. Moreover, FIG. 10(B) indicates the control in the case of the synchronous DRAM (hereinafter referred to as SDRAM) in which the self-refresh operation is executed with a command input synchronized with a clock signal CLK. The self-refresh operation is started with a start command REF of the refresh operation and thereafter the self-refresh state is maintained. When a command EXIT is issued, the self-refresh state is canceled.
During the period of the self-refresh operation, an external access operation such as read and write of data is never conducted ((I) of FIG. 10) and the refresh operation as the internal access operation is continued. A count-up signal COUNT of a refresh address counter is outputted to a refresh-operation-start request signal REQ (I) which is outputted in the predetermined refresh period and a refresh address signal Add (C) is sequentially incremented. Thereafter, a refresh executing signal is outputted based on the refresh-operation-start request signal REQ (I) and the refresh operation is sequentially executed to the memory cell areas (memory cells connected to the predetermined word lines) indicated with the refresh address signal Add (C).
An ordinary self-refresh operation in the related art explained above is always controlled with the external control signals /RAS, /CAS or with the external commands REF, EXIT exclusive of the external access operation such as data read and write operations. Therefore, during the self-refresh operation period, the refresh-operation-start request signal REQ (I), count-up signal COUNT, refresh address signal Add (C) and refresh executing signal are respectively corresponding to each other on 1:1 basis and the address areas indicated by the refresh address signal Add(C) which is sequentially incremented in every refresh period is then sequentially selected.
In recent years, as a result of diversification of the functions required for the mobile devices with the rapid development thereof, the static random access memory (hereinafter referred to as SRAM) which has been loaded to the predecessors is now replaced with further large capacity memory. Therefore, from the necessity to load a large capacity memory explained above in the practical price in the limited space, a DRAM with built-in refresh function which is so-called a pseudo SRAM has been used. That is, a pseudo SRAM for controlling the refresh operation peculiar to the memory cell of DRAM or the like which assures high integration density and low bit price is built-in. Moreover, as a means to realize a synchronous SRAM (hereinafter referred to as SSRAM) with a memory cell of SDRAM for the requirement of high speed operation in future, the specification for the pseudo SSRAM has become a practical means in current.
Since the pseudo SRAM or pseudo SSRAM assures compatibility with SRAM or SSRAM in the circuit operations, it is specified to automatically execute the refresh operation whenever it is required. Therefore, the refresh operation as the internal access operation and an ordinary data read/write operation as the external access operation are executed independently in the desired timing.
FIG. 11 shows waveforms in the external access operation and the refresh operation of the pseudo SRAM in the related art. Since the refresh operation as the internal access operation is executed independent of the read/write operation as the external access operation, arbitration is required when both operations are overlapped. (II) of FIG. 11 indicates the overlap of the single refresh operation and external access operation. An external-access-start request signal REQ (O) is outputted with a delay from a refresh-operation-start request signal REQ (I). When the single refresh operation and single external access operation are overlapped, arbitration of access operation is conducted to execute any one single operation with a priority and then execute later the other single operation with a certain delay. In FIG. 11, the refresh operation for the refresh address #1 is executed with the priority and thereafter the external access operation is conducted for the address #b. The refresh operation is executed without any delay to the refresh-operation-start request signal REQ (I). Meanwhile, the external access operation is executed with a certain delay from the external-access-start request signal REQ (O).
(III) of FIG. 11 indicates the external successive access operation such as a page operation to be executed bridging over the refresh operation. The refresh-operation-start request signal REQ (I) is issued during the period of the continuous external-access-start request signal REQ (O). In general, since a high speed continuous access operation is required in the external successive access operation, execution of the refresh operation is inhibited until such continuous operation is completed and the arbitration is conducted to execute the refresh operation following the completion of the external successive access operation. The external successive access operation is executed with priority for the addresses #c to #c+k and thereafter the refresh operation is executed for the refresh address #3. The external successive access operation is executed without delay for the external-access-start request signal REQ (O). On the contrary, the refresh operation is executed with a delay from the refresh-operation-start request signal REQ (I).
Moreover, a mobile device is often placed under the standby state for a longer period such as a mobile phone and a digital camera, etc. and therefore this mobile device is always required to reduce the current dissipation up to the ultimate extent in the standby state in order to improve the continuous duration time characteristic while the device is operated with a battery. Therefore, it is an essential matter for a DRAM or the like to reduce the current dissipation in the refresh operation such as the self-refresh operation which is periodically conducted even during the standby state. As a method to reduce the current dissipation during the refresh operation, two kinds of methods, one is the refresh-thinning-out operation and the other is the partial refresh operation, have been proposed.
FIG. 12 shows the waveforms in the refresh operation corresponding to the refresh-thinning-out operation. In the case of the memory cells loaded to a semiconductor memory device, its electrical characteristic is generally given a predetermined width. The data holding characteristic stored in the memory cells also has a predetermined width and the refresh period tRF of the refresh operation must be set for the worst value of the data holding characteristic. Meanwhile, for the memory cells having the excellent data holding characteristic, it is enough when the refresh operation is executed in the period longer than the preset refresh period tRF. Therefore, it is set for the memory cells having excellent data holding characteristic that the refresh operation is conducted once for every two periods of the refresh period tRF. Thereby, the number of refresh operations per predetermined time is reduced and accordingly the current dissipation in the refresh operation can also be reduced.
In FIG. 12, the memory cells of the refresh address #1 correspond to such memory cells. The refresh operation is inhibited once for every two periods to execute the control of the refresh-thinning-out operation. For the control of the refresh-thinning-out operation, matching/miss-matching of address must be judged by previously storing the addresses of the memory cells having the excellent data holding characteristic to the internal storage means and then comparing such addresses with the refresh address signal Add(C) from the refresh address counter which is counted up for every refresh-operation-start request signal REQ (I). When the addresses are matched as a result of comparison, a comparison signal CMP is inverted to the high logic level to inhibit the refresh operation. Therefore, it is necessary prior to output of the refresh executing signal to count up a refresh counter with a count-up signal COUNT depending on the refresh-operation-start request signal REQ (I).
FIG. 13 shows the waveforms of the refresh operation corresponding to the partial refresh operation. In this partial refresh operation, the refresh operation is not executed to the predetermined memory cell region in the semiconductor device but only to the memory cell region which requires the data holding. Thereby, the number of the refresh operations per predetermined time can be reduced and the current dissipation in the refresh operation can also be lowered.
In FIG. 13, the memory cell areas of the addresses #k to #k+2 correspond to such partial refresh operation. The refresh operation is inhibited to these address areas but is executed to the other addresses. The control for inhibiting the refresh operation is executed in the same manner as the control for the refresh-thinning-out operation. Matching/miss-matching of address is judged by storing the addresses of the memory cell region which do not require the holding of data to the internal storage means and then comparing these addresses with the refresh address signal Add (C) from the refresh address counter which is counted up in every refresh-operation-start request signal REQ (I). When the addresses are matched as a result of comparison, a comparison signal CMP is inverted to a high logic level to inhibit the refresh operation. Therefore, it is necessary to count up the refresh address counter with a count-up signal COUNT depending on an output of the refresh-operation-start request signal REQ (I) prior to an output of the refresh executing signal.
However, there is a fear for generation of a couple of operational problems explained below when the external access operation and refresh operation are to be executed independently in the pseudo SRAM and pseudo SSRAM while reduction of current dissipation is realized in the standby state through the refresh-thinning-out operation and partial refresh operation. Therefore, when the semiconductor memory device which requires the refresh operation of DRAM and SDRAM or the like is used in the compatible specification for the SRAM of the pseudo SRAM and pseudo SSRAM as the semiconductor memory device for use in mobile devices, a problem rises here because it is impossible to simultaneously realize the low current dissipation performance in the standby state due to the refresh-thinning-out operation and partial refresh operation and the access performance of a large capacity data or high speed data access performance, which are executed independent of the refresh operation.
A first problem is illustrated in FIG. 14. With realization of further sophisticated system, the high speed transfer ability of a large capacity data is required and improvement in the data occupation rate of the I/O bus in the system is also required. In this case, the external successive access operation such as the random page operation and burst operation or the like is required to be continued for a long period of time. This continuation period is also considered to be lasted exceeding a plurality of refresh periods.
FIG. 14 illustrates an example wherein the external successive access operation is continued for the three refresh periods while the external address Add (O) is sequentially switched for the external successive access operation which is set by inputting a setting signal ((A) in FIG. 14) or the predetermined command to the predetermined external terminal. During these three periods, the refresh operation is inhibited. However, the count-up signal COUNT is outputted for the three outputs of the refresh-operation-start request signal REQ (I) and thereby the refresh address signal Add (C) is incremented (address #1 to #3). Since the refresh-thinning-out operation and partial refresh operation are set here, the refresh address counter is incremented together with the refresh-operation-start request signal REQ (I).
In this case, since improvement in high speed data transfer ability and I/O bus occupation rate is requested, the refresh operation due to the refresh-operation-start request signal REQ (I) generated during the external successive access operation is executed after the completion of the external successive access operation. However, if the external successive access operation period continues exceeding the three refresh periods, the address of the refresh operation to be executed after the external successive access operation becomes the refresh address #3 which is set by the three times of count-up. For the refresh addresses #1 and #2 before the address #3, the refresh operation is not executed until the timing of the next refresh operation after one refresh cycle. When the external successive access operation is executed in the timing of the next refresh operation, this access operation is extended further, in a certain case, up to the next refresh operation timing. Therefore, here rises a problem that there is a fear that the data may be lost during this period.
FIG. 15 illustrates a second problem. In the case where the high speed data access is required as the system function is further sophisticated, it is also considered that it may be necessary to set with priority the external access operation without influence of the refresh operation.
In FIG. 15, a semiconductor memory device such as a pseudo SRAM or the like is assumed as a device having the function to set the external-access operation priority mode with an input of the setting signal or the predetermined command to the predetermined external terminal. Even when the external-access operation priority mode is set to inhibit the refresh operation, the count-up signal COUNT is outputted for each output of two refresh-operation-start request signals REQ (I) and thereby the refresh address signal Add(C) is incremented (address #1, address #2). The reason is that since the refresh-thinning-out operation and partial refresh operation are set, the refresh address counter is incremented together with the refresh-operation-start request signal REQ (I).
In this case, since the high speed data access performance is requested, the refresh operation due to the refresh-operation-start request signal REQ (I) generated in the external-access operation priority mode period is executed after the setting of the external-access operation priority mode is canceled. However, when the period of the external-access operation priority mode continues exceeding the two refresh periods as explained above, the address of the refresh operation to be executed after the external-access operation priority mode is canceled becomes the refresh address #3 which is set with the subsequent count-up. For the refresh addresses #1, #2 before the address #3, the refresh operation is not executed until the timing of the next refresh operation after one refresh cycle. When the external-access operation priority mode is set in the timing of the next refresh operation, the refresh operation is further delayed in a certain case until the timing of the next refresh operation. Here, a problem also rises here that the data may be lost during this period.
The present invention has been proposed to overcome the problems of the related arts and it is therefore an object of the present invention to provide a semiconductor memory device and a refresh control method which can execute the refresh operation which may be surely realized without any problem for the external access while realizing a low current dissipation on the occasion of executing the refresh operation as the internal access operation independent of the external access operation.
According to one aspect of the present invention, there is provided a refresh control method of semiconductor memory device comprising an external access operation executed based on an external request and a refresh operation executed internally and automatically, wherein the number of generations of the refresh operation start request is monitored during the period of the external access operation executed with priority to the refresh operation, and the internal operation in the refresh operation is controlled depending on the number of generations of the refresh operation start request.
Moreover, according to one aspect of the present invention, there is also provided a semiconductor memory device executing an external access operation based on an external request and a refresh operation which is conducted therein automatically, comprising: an in-operation-state informing section for informing the in-operation-state of the external access operation and the refresh operation; and a refresh-operation-start request generating section for outputting a refresh-operation-start request signal; and a monitoring section for monitoring, when the in-operation-state informing section is informing the in-operation-state of the external access operation, the number of generations of the refresh-operation-start request signal to control the internal operation in the refresh operation depending on the number of generations of the refresh-operation-start request signal.
In the semiconductor refresh control method and such semiconductor memory device, even when the refresh-operation-start request signal is generated to request the start of the refresh operation during the period of the external access operation to be executed with priority to the refresh operation, the internal operation in the refresh operation is controlled depending on the number of generations of such refresh-operation-start request signal.
Thereby, even during the period of the external access operation which is executed with priority to the refresh operation, the control state of the internal operation required for the refresh operation is held as required and thereby the subsequent refresh operation can surely be executed.
Moreover, according to another aspect of the present invention, there is also provided a refresh control method of semiconductor memory device comprising an external access operation executed based on an external request and a refresh operation executed internally and automatically, wherein the number of generations of the refresh operation start request is monitored during the period in which execution of the refresh operation is inhibited because the external access operation is executed with priority depending on the setting from the external, and the internal operation in the refresh operation is controlled depending on the number of generations of the refresh operation start request.
Moreover, according to another aspect of the present invention, there is also provided a semiconductor memory device executing an external access operation based on an external request and a refresh operation which is conducted therein automatically, comprising: an inhibition-setting informing section for informing the execution-inhibiting-state of the refresh operation based on an external execution-inhibiting setting of the refresh operation; a refresh-operation-start request generating section for outputting a refresh-operation-start request signal; and a monitoring section for monitoring, when the inhibition-setting informing section is informing the execution-inhibiting-state of the refresh operation, the number of generations of the refresh-operation-start request signal to control the internal operation in the refresh operation depending on the number of generations of the refresh-operation-start request signal.
In the semiconductor memory device refresh control method and the semiconductor memory device, even when the refresh-operation-start request signal is generated to request the start of the refresh operation during the period in which execution of the refresh operation is inhibited due to the external setting, the internal operation in the refresh operation is controlled depending on the number of generations of such refresh-operation-start request signal.
Accordingly, the internal operation control state required for the refresh operation can be held as required even during the period in which the refresh operation is inhibited due to the external setting and thereby the subsequent refresh operation can surely be executed.
The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.